1. Field of the Invention
The present invention relates to a layout design method for a semiconductor integrated circuit.
2. Description of the Related Art
There has been developed a layout design method that designs the layout of a semiconductor integrated circuit. The semiconductor integrated circuit is equipped with a hard macro that is disposed on a chip, and a passing wiring. When the hard macro is a memory macro, a DRAM (dynamic random access memory) macro and an SRAM (static random access memory) macro have been widely known. In the design method, the passing wiring is arranged on an upper layer of the hard macro as a macro outer wiring with respect to the layout data in which the hard macro is arranged in a coordinate region. However, there is a risk that the hard macro malfunctions due to an influence of the noises depending on a portion where the passing wiring is arranged. For that reason, a given region within the hard macro is regarded as a wiring obstruction region (OBS), the passing wiring on the hard macro is obstructed, and the passing wiring bypasses the hard macro, thereby making it possible to reduce an influence of the noises.
In recent years, higher integration has been further demanded on the semiconductor integrated circuit. The higher integration leads to an increase in the number of passing wirings. However, when all of the passing wirings bypass the hard macro, a region for the bypassed passing wirings needs to be ensured, which interferes with the higher integration. Under the circumstances, a part of passing wirings is disposed on the hard macro, and other passing wirings bypass the hard macro, thereby making it possible to reduce an influence of the noises without preventing the higher integration.
For example, JP Hei 10-107149A discloses a technique in which attributes are given the hard macro and all of the passing wirings (net). In the technique, the passing wiring whose attribute coincides with the attribute of the hard macro among all of the passing wirings is disposed on the hard macro, and other passing wirings bypass the hard macro. In the case where the attribute of the passing wiring coincides with the attribute of the hard macro, as the attribute of the passing wiring, there are attributes that a voltage level represented by a signal which is transmitted from the passing wiring is held constant, that the signal is synchronous with the operation of the hard macro, and that the passing wiring is a test signal line.
Also, JP Hei 11-145296A discloses a technique in which the bypass wiring is arranged within the hard macro in advance as a method of inhibiting the passing wiring on the hard macro, and preventing the passing wiring from bypassing the hard macro. In that technique, in the case where the hard macro exists on a line that connects one block and another block when the passing wiring extends from the one block to the another block, the passing wiring from the one block is connected to one end of the bypass wiring, and the passing wiring from the another block is connected to another end of the bypass wiring.